1. Field of the Invention
The present invention relates to circuitry for switching electrical signals transmitted from one location to another. More particularly, the present invention relates to switch circuitry for translating electrical signals at a first potential into corresponding electrical signals at a second potential different from the first potential. The present invention includes a disablement option for selective activation of the translation switch circuitry.
2. Description of the Prior Art
Output buffers are used to transfer electrical signals of desired amplitude and strength. Signal transfers occur by way of busesxe2x80x94interfaces that couple together active devices that are either on the same semiconductor-based chip or on different chips. The devices may be located proximate to one another, or they may be some relative distance from one another. Among other uses, output buffers including those employed to translate electrical signals on a particular computing system board or among a plurality of circuit boards of a computing system.
Developments in semiconductor technology have created the capability to produce low-cost, highly reliable switches that are, effectively, implementations of mechanical relays. They have been found to be of particular use, when implemented, as single pole, single throw, type relays, but are not limited thereto. Semiconductor switches are used as replacements for the prior mechanical relays, due to the high switching speed available as well as their ability to transfer relatively high currents without failure. These switches are often referred to as transfer gates or pass transistors as they employ the characteristics of transistorsxe2x80x94usually MOS transistorsxe2x80x94to either permit or prevent the passage of a signal.
It is well known that semiconductor switches are widely used in many fields. They are used in all variety of large- and small-scale consumer products, including, but not limited to, automobiles and home electronics. They can be and are used as analog routers, gates, and relays. They are used as digital multiplexers, routers, and gates as well.
A number of prior-art transfer gates or semiconductor switches have been developed for digital and analog applications. These switches are increasingly being called upon to transfer electrical signals to systems that are powered by power supplies at potentials different from the potentials associated with the input electrical signals. As a result, it is necessary to have switches that can convert or translate electrical signals at one potential to corresponding signals at a different potential, at least with respect to the potential associated with a logic HIGH. As is well known by those in this field, the difference in the potentials associated with a logic HIGH signal and a logic LOW signal may be as small as 0.4V or as great as 5V. For Complementary Metal Oxide Semiconductor (CMOS) based logic for example, a logic high corresponds to a nominal 5.0V potential (for a 5.0V power supply) and a nominal 3.3V potential (for a 3.3V power supply), while a logic low is essentially equivalent to ground (GND) or 0.0V.
The potentials associated with HIGH and LOW signals described above are idealized values. In fact, the signal potentials generally fall within a range of potentials associated with the indicated values. Thus, for a 3.3V supply, a HIGH signal may be supplied at 2.6V, for example, while a LOW signal may actually be associated with a 0.7V value. As the potentials of the power supplies used to power circuitry move closer to GND, variations in signal potentials are more likely to produce transmission glitches. It is therefore desirable to maintain signal potentials as stable as possible. Alternatively or in addition, it is important to design the semiconductor switch to be less sensitive to signal variations but without sacrificing operating capability, i.e., propagation rates and signal amplitudes. This is particularly noteworthy for translation circuitry where the disparity in logic HIGH potentials can be on the order of 1.7V as indicated above.
One example of a typical potential translating bus switch is shown in FIG. 1. The bus 1 includes a set of 12 switch structures SW1-SW12, each of which is designed to transfer a bit of information from individual input nodes a1-a12 to corresponding individual output nodes b1-b12. Nodes a1-a12 are coupled to extended circuitry (not shown) having a power supply at a first potential and nodes b1-b12 are coupled to extended circuitry (not shown) having a power supply at a potential less than that of the extended circuitry coupled to nodes a1-a12. Of course, it is to be understood that the bus may comprise more or fewer switch sets as a function of the number of bits to be propagated.
As illustrated in FIG. 2, an exemplar one of the switch structures, switch SW1, is shown coupled between node a1 and node b1. The other switch structures may be similarly configured. Extended circuitry coupled to node a1 is powered by a high-potential supply Vcc1 and extended circuitry coupled to node b1 is powered by a high-potential supply Vcc2 that is less than the potential associated with Vcc1. Both are coupled to a common low-potential rail GND.
The switch SW1 includes a transfer transistor M1 having a source coupled to node b1 and a drain coupled to node a1. The transistor M1 is preferably an NMOS transistor. The transfer transistor M1 is designed, when enabled by a transfer switch-enabling signal at enable node EN, to propagate electrical signals from node a1 to node b1. The transfer transistor M1 includes a bulk or backwell coupled to a low-potential power rail GND that is common to the extended circuitry associated with nodes a1 and b1. The switch SW1 further includes a first inverter IV1 and a second inverter IV2. The first inverter IV1 is coupled between Vcc1 and GND and includes an input coupled to node EN. Second inverter IV2 includes a complementary pair of inverter transistors M2 and M3. Transistor M2 is a PMOS transistor having a gate coupled to the output of IV1, a source coupled to a pseudo high-potential power rail Prail, and a drain that is, effectively, node C. Transistor M3 is an NMOS transistor having its gate also coupled to the output of IV1, its source coupled to GND, and its drain coupled to node C. The potential of Prail establishes the potential of the output of IV2 to the gate of M1 and so by definition is less than the potential of Vcc1.
With continuing reference to FIG. 2, the potential of Prail is established in the prior art by a diode drop across diode D1. Diode D1 has a high potential node coupled to Vcc1 and a low-potential node coupled to resistor R. The output of forward-biased diode D1 supplies a potential to the source of M2 that is transferred, with a second drop associated with that transistor, to the gate of M1. That arrangement is sufficient to produce a suitable translation of the signal potential from a1 to b1.
Unfortunately, the design of the switch circuit as shown in FIG. 2 has an important limitation if there is any interest in using the switch to propagate transient signals rather than steady state signals. Specifically, noise on Prail that changes the potential of that rail can result in translation errors at the corresponding b nodes when logic signal transitions occur. That noise is caused by multiple simultaneous logic-LOW-to-logic-HIGH transitions on the inputs al-a12. The noise causes current to be injected onto Prail through the drain/gate capacitance of the corresponding large transfer transistor represented by transistor M1 in FIG. 2. As the voltage on one side of the effective capacitor of that transistor changes, the voltage on the other side of the capacitor also changesxe2x80x94unless it is fixed to a power rail or a voltage reference.
Diode D1 will not restrict the voltage changing on the gate of transistor M1. Resistance R acts to restrict the voltage change in a sense, but it has much lower impedance than the effective capacitor at edge rate frequencies of interest. As a result, the voltage on the gate of transistor M1 will rise. For each of the inputs, the gates of the respective primary translation transistor will attempt to rise with a LOW-to-HIGH transition. That potentially detrimental rise is magnified when multiple inputs switch substantially simultaneously, rendering the likelihood of overshoot more possible. There is a time delay associated with that overshoot. That time delay is defined by the RC time constant associated with the parasitic capacitance associated with the diode clamp, the gate capacitance of M1, and the capacitance of driver circuitry. The delay is unacceptable when it exceeds the switching rates desired in transition-capable switches. For that reason, many switch circuits such as that shown in FIG. 2 are less than suitable for adequate switching of transient signals.
Therefore, what is needed is a translation switch circuit that includes a pseudorail potential generator suitable for establishing a potential level suitable for the translation of an electrical signal at one potential to an electrical signal of the same logic condition but at a lower potential. Further, what is needed is such a translation switch circuit having the means to clamp the pseudorail potential at a desirable level including under transient noise conditions on that rail during signal rising edges. The switch circuit with those characteristics relatedly includes means to rapidly remove excess current from the pseudorail with very little delay so that the translation circuit may be employed to propagate transient translation signals. More generally, it would be desirable to have a translation switch circuit that may be selectably enabled for translation of the signal from the input node to the output node when required, but that would otherwise permit propagation of an electrical signal between those nodes without translation.
It is an object of the present invention to provide a translation switch circuit that includes a pseudorail potential generator suitable for establishing a potential level suitable for the translation of an electrical signal at one potential to an electrical signal of the same logic condition but at a lower potential. Further, it is an object of the present invention to provide a translation switch circuit having the means to clamp the pseudorail potential at a desirable level including under transient noise conditions on that rail during signal rising edges. It is another object of the present invention to provide a translation switch having the means to rapidly remove excess current from the pseudorail with very little delay so that the translation circuit may be employed to propagate transitioning translation signals. More generally, it is another object of the present invention to provide a translation switch circuit that may be selectably enabled for translation of the signal from the input node to the output node when required, but that otherwise permits propagation of an electrical signal without translation.
These and other objects are achieved in the present invention by the introduction of an active clamping element to the pseudorail generator circuit to replace the passive resistance device described with respect to the switch of FIG. 2. Specifically, the clamping element is designed to be barely on when the switch is operational. As current on the pseudorail increases, the clamping element is turned on more completely. It is preferably designed to be a current amplifier and so it will sink current from the pseudorail much more quickly than is possible with a resistance. Although a variety of arrangements of the clamping element are described more fully herein, one preferably arrangement includes a MOS transistor in combination with a bipolar Darlington pair. That combination generates little power consumption when the current feedback from the pseudorail is stable, but it can very quickly sink current when noise on that rail threatens to disrupt the translation of the electrical signal propagated from one node to another. Moreover, the combination does not adversely impact the standard functionality of the pseudorail in that it provides the necessary potential drop from the potential of the higher supply rail to the gate of the transfer transistor of FIG. 2. The active clamping element permits the translation switch circuit that includes it to be used for transient as well as steady state signal translation. The active clamping element of the present invention may be deployed as a single circuit associated with a single pseudorail that may be used with a plurality of switches in parallel. Alternatively, a plurality of switches may be coupled each to their own pseudorail and corresponding active clamping element. Using a single active clamping mechanism for each switch ensures that each switch would be isolated from one another. When coupled in parallel to the pseudorail, there may be linkage among the switches.
A related but distinct aspect of the present invention is a translation disabling means to be used when the switch circuit is not required to translate an electrical signal from a first potential to a lower second potential. It is desirable in some instances to be able to provide a switch circuit of generic design that may be employed in situations where translation is required and in situations where it is not. For that reason, the present invention includes a biasing bypass circuit that has an output coupled to the pseudorail. However, rather than providing at least one diode drop to that pseudorail, the bypass circuit couples the pseudorail directly to the high potential supply rail. The input to the bypass circuit is coupled to control logic for disablement of the potential reducing generator when the potential to the gate of the transfer transistor is to be substantially full rail-to-rail. Otherwise, the pseudorail generator operates as indicated. However, it is to be understood that the bypass circuit may be employed in combination with any sort of current regulator for the pseudorail. Specifically, it may be used with a circuit such as the prior-art switch of FIG. 2 or it may be used with an active clamping element such as those described herein.